Design and Simulation of UART IP Core for FPGA Implementation
نویسندگان
چکیده
Universal Asynchronous Receiver Transmitter (UART) is a popular two wire serial communication interface between two microcomputer based systems. The programmable logic devices can be used for such application by developing core for UART. This design included transmitter, receiver and baud rate generator. By using hardware descriptive language UART simulation can be tested before it can be loaded on programmable device. In simulation and results part, this paper will describe the functionality of UART. From the designing point of view, we can say that this design is most efficient and cost effective.
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